1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same, and more particularly, to a trench-type gate of a dynamic random access memory (DRAM) and a method of forming the same.
2. Description of the Prior Art
A dynamic random access memory (DRAM) is one kind of volatile memory. A DRAM usually includes an array region including a plurality of memory cells and a peripheral region including control circuits. Typically, a memory cell includes one transistor and one capacitor electrically coupled to the transistor, which is known as a 1T1C cell. A digital data is stored in a memory cell by controlling the transistor to charge or discharge the capacitor. The control circuits in the peripheral region may address each of the memory cells in the array region by plural columns of word lines and plural rows of bit lines traversing the array region and electrically connected to each of the memory cells to perform reading, writing or erasing data.
In advanced technology node of semiconductor manufacturing, the dimension of a memory cell has been miniaturized for higher integrity by adopting three-dimensional structure. DRAMs having buried word line structures have been proposed and widely used in the field in which gate electrodes of transistors and word lines for controlling the transistors are formed integrally in a plurality of trenches formed in the substrate and traversing through the active regions. The transistors are trench-type gates formed at the overlapping region between the active regions and the trenches. The advantages of using buried word line structures may include improved speed and higher integrity. The leakage current resulting from the short channel effect as device shrinking may be avoided.
However, there are still some problems need to be overcome when adopting buried word line structure. For example, drain induced gate leakage (GIDL) is a serious problem for DRAMs having buried word line structures. GIDL is caused by overlapping between the source/drain region and the gate electrode of the transistor. Some attempts have been made in the field to eliminate GIDL including recessing the top surface of the gate electrode to a lower level in the trench thereby increasing the distance between the source/drain region and the gate electrode. However, the resistances of the gate electrode and the channel region may adversely increase, causing degradation of performance. Another method for avoiding GIDL is increasing the thickness of the gate dielectric layer which lines the trench and between the gate electrode and the substrate. However, thicker gate dielectric layer would unfavorably decrease the on-current (Ion) and consequently degrade the switching speed of turned-on and turned-off. Therefore, there is still a need in the field to provide a trench-type gate with reduced GIDL and better performance.